Ordinarily, a semiconductor device or integrated circuit ("IC") is designed such that data and control input signals are received simultaneously and subsequently processed by an internal logic circuit ("internal logic"). Before such an input signal is applied to the internal logic, it is amplified by a input buffer or receiver to have a sufficient driving power. To enable the IC to execute an expected signal processing, each input receiver is required to transfer a logic value of the input signal to the internal logic without error. Therefore, it is important that a threshold voltage of the input buffer be within predetermined limits specified by the IC manufacturer. To ensure that an input pin's drive capability conforms to the manufacturer's specified limits, input voltage measurement tests are routinely performed, for example, during outgoing DC parametric production test by the IC or system manufacturer.
The input voltage level test consists of two measurements on each of the input and bidirectional I/O pins, namely, VIH and VIL measurements. In a conventional test for the threshold voltage of the receiver in an IC, to confirm that a pin meets an input voltage level, a tester drives the pin with a voltage equal to the lowest specified voltage that is to be interpreted as logic value one in the case of a VIH test or a voltage equal to the highest specified voltage that is to be interpreted as logic value zero in the case of a VIL test. It then gathers and compares the response from the IC output pins. If the response matches the expected response, the receiver at the input or I/O pin under test is believed to have properly interpreted the input voltage. That pin is declared to have passed the particular input voltage test (i.e., VIL or VIH test) being performed.
While the VIH/VIL test is fairly simple in theory, it is difficult to implement because the logic value sensed by the tested pin's receiver is not observable and the pass/fail determination must be made indirectly based on the response of an IC's internal logic. The test is made even more difficult and tedious if isolation of the failing pin is desired or actual voltage limits are measured. In such cases, it is necessary to write several tests, each feeding only one input pin with the test voltage level while applying all other inputs with their full normal voltage levels. The test pattern applied by the test must sensitize the effect of voltage level sensed at the pin under test to an observable output.
To simplify the input threshold voltage test, prior test techniques have utilized the testability features of the Standard Test Access Port and Boundary-Scan Architecture or IEEE Std 1149.1 (hereinafter, the "Standard") now built into most ICs. In general, the Standard provides for the design of ICs in a standard fashion such that their internal or their external connections (or both) may be tested using a standard 4-wire bus interface known as the Test Access Port ("TAP"). While not defining every detail of Standard-compliant (or, alternatively, boundary-scan-compliant) circuits, the Standard does specify minimum requirements to be met by every boundary-scan-compliant component, whether it be a circuit board or an IC. Complete details of the Standard may be had with reference to the publication entitled "IEEE Standard Test Access Port and Boundary-Scan Architecture," published by the Institute of Electrical and Electronics Engineers, Inc. (1993).
The boundary scan architecture of the Standard involves a number of boundary scan cells (BSCs) inside each boundary-scan-compliant component corresponding to and connected to the buffer outputs of each of the component's input pins and output pins so that signals at the component's boundaries can be controlled and observed. The cells are interconnected to form a shift register chain around the border of the component. This interconnected path, referred to as a boundary scan register, and alternative paths consisting of either a test instruction register or other test data register, are provided with a serial input and output connection and appropriate clock and control signals via the Test Access Port. Using these data and test instruction "scan" paths, test instructions and associated test data can be fed or shifted into the component. The results of the execution of an instruction can be read out via the serial output connection.
The test instruction, once loaded into the instruction register and decoded by decode logic, selects the operational mode of the boundary scan cells and the data register to be used for a given test. A boundary-scan-compliant component must support a set of mandatory instructions, including SAMPLE/PRELOAD and EXTEXT.
SAMPLE/PRELOAD allows a boundary scan register to be initialized prior to selecting other instructions such as EXTEST. EXTEST allows testing of board-level interconnections and off-chip circuitry. Test data is shifted into the BSR and applied to the output pins in parallel. A test result appearing at the input pins is captured into the BSR in parallel and shifted out serially.
Also connected to the TAP is a TAP controller state machine and dispatch logic. The state machine interprets the Standard protocols received on the TAP control lines and the dispatch logic decodes the states and causes specific actions (e.g., capture, shift, update) to occur in the various registers.
As previously mentioned, the boundary scan architecture may be utilized to perform input threshold voltage testing. In response to certain clock and control signals provided at the TAP and test voltages applied to input pins by external test control circuitry, the test voltages sensed by the input pins are loaded into corresponding boundary scan cells and shifted out of the boundary scan register for examination. The capturing and shifting operations are achieved by following the Standard's protocols. Therefore, with this VIH/VIL testing approach, all input pins can be tested simultaneously yet individually to isolate failing pins.
For example, the VIH level test using a component's boundary scan register may be performed in the following manner. First, via the Standard defined SAMPLE/PRELOAD instruction, the boundary scan cells on all input pins are initialized to zeroes. Boundary scan cells controlling the direction of bidirectional I/O pins (i.e., "control cells") are also initialized such that the I/O pins they control are configured as input pins. Next, the Standard defined EXTEST instruction is loaded and the VIH test voltage is applied to all input pins and I/O pins. The TAP controller is caused to step through a data scan sequence to capture pin states and shift out the contents of the boundary scan register for observation. Once the VIH test is completed (i.e., the output is compared to an expected value and a pass/fail indication given for each input), the boundary scan register is prepared for the VIL test. This time, the boundary scan cells at all inputs are loaded with ones. The VIL test voltage is then applied to the input pins and I/O pins and the data scan sequence repeated.
In many high performance ICs, e.g., the ALPHA.TM. 21264 microprocessor available from Digital Equipment Corporation, it has been possible to achieve a higher bandwidth at the input interface or boundary by employing a forwarded clock interface. Clock forwarding techniques are discussed generally in U.S. Pat. No. 4,979,190, issued to Sager et al. Unfortunately, the use of a forwarded clock interface adversely impacts compliance of the boundary scan register with the Standard. For example, in a "high-end" forwarded clock interface, a data input pin may be coupled to two latch receivers each clocked by a forwarded clock. One latch receiver samples data on the rising edge of the forwarded clock while the other on the falling edge of the forwarded clock. A BSC located on such an input pin would violate the Rules 10.4.1e and 10.5.1i of the Standard, as its input capture path has a dependency on another input, namely the forwarded clock.
Of course, one may consider forcing one of the latch receivers to open during the boundary scan operation and using it to source the capture data; however, this solution works only if the latch receivers are level sensitive and not edge triggered. Besides, it has two serious shortcomings. First, it introduces undesired delay and skew in the sensitive clock path. Second, it does not cover the VIH/VIL testing of the second receiver, unless an elaborate provision is made to jam the clock enable to the other value.
Therefore, there exists a clearly felt need in the art to provide a scheme which allows for the input threshold voltage testing of each clocked receiver at a system data input of a forwarded clock interface using boundary scan testability features, but maintains compliance with the Standard for the execution of Standard-defined test operations.